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Learning Resources

A curated list of resources for learning CUDA programming and GPU kernel optimization.

Suggested reading path

If you are using TensorCraft-HPC as a learning project or interview artifact, this order works well:

  1. Read the project whitepaper to understand the repository's design intent.
  2. Use this page to branch outward into the core NVIDIA references and neighboring open-source projects.
  3. Return to the repository's architecture overview and kernel atlas with that external context in mind.

This makes the project easier to compare honestly against production libraries and research-grade implementations.

Official NVIDIA Resources

Documentation

Libraries

  • cuBLAS — Dense linear algebra
  • cuDNN — Deep learning primitives
  • cuSPARSE — Sparse linear algebra
  • NCCL — Multi-GPU communication

Tools


Open Source Projects

Kernel Libraries

ProjectFocusDifficulty
CUTLASSGEMM, Tensor CoresAdvanced
FlashAttentionAttentionAdvanced
xFormersAttention, MemoryIntermediate
TritonDSL for kernelsIntermediate
DeepSpeedTraining optimizationAdvanced

How these projects relate to TensorCraft-HPC

ProjectWhy compare itWhat TensorCraft-HPC emphasizes instead
CUTLASSCanonical CUDA GEMM / Tensor Core engineeringSimpler learning path and clearer optimization narration
FlashAttentionReference-quality attention implementationEasier-to-follow explanation of tiling and memory trade-offs
TritonAlternative kernel authoring modelDirect C++/CUDA control and closer-to-metal educational examples
xFormers / DeepSpeedReal-world training-system contextFocused operator learning rather than full-stack training infrastructure

Educational

ProjectDescription
CUDA ModeCUDA learning resources
GPU ModeGPU programming tutorials
Awesome CUDACurated CUDA resources

Books

GPU Programming

  • Programming Massively Parallel Processors — David B. Kirk, Wen-mei W. Hwu
    • The classic textbook for GPU computing
  • CUDA by Example — Jason Sanders, Edward Kandrot
    • Practical introduction to CUDA
  • Professional CUDA C Programming — John Cheng, Max Grossman, Phil McGachey
    • Advanced CUDA techniques

Computer Architecture

  • Computer Architecture: A Quantitative Approach — Hennessy & Patterson
    • Understanding memory hierarchies and parallelism

Online Courses


Key Concepts

Memory Hierarchy

Execution Model

Optimization Priority

  1. Maximize Parallelism — Enough threads to hide latency
  2. Coalesced Memory Access — Adjacent threads access adjacent memory
  3. Shared Memory Usage — Reduce global memory traffic
  4. Bank Conflict Avoidance — Ensure shared memory efficiency
  5. Occupancy Tuning — Balance registers, shared memory, threads

What to borrow into this project

When expanding TensorCraft-HPC, the most valuable ideas to absorb from the surrounding ecosystem are:

  • from CUTLASS: disciplined tiling vocabulary and Tensor Core decomposition patterns
  • from FlashAttention: memory-aware storytelling and IO-driven reasoning
  • from Triton: clear operator-level benchmarking habits and compact examples
  • from Nsight tooling: evidence-first performance explanations instead of intuition-led guesses

What to borrow, what to resist

The repository becomes stronger when it borrows methods, not when it imitates style blindly.

Borrow

  • disciplined vocabulary for tiling, memory traffic, and hardware capability
  • benchmark methodology that exposes caveats and baselines
  • compact operator examples that map cleanly to the public API

Resist

  • production-only abstractions that hide the optimization path
  • feature sprawl that makes the educational story harder to follow
  • benchmark claims separated from tooling, workload shape, or reference library

This tension is intentional. TensorCraft-HPC should learn from stronger systems without becoming another opaque production stack.


Performance Metrics

MetricDescriptionTarget
ThroughputOperations per secondRoofline limit
LatencyTime per operationMinimal
OccupancyActive warps / Max warps50-100%
Memory BandwidthBytes transferred / second~90% peak
Compute EfficiencyAchieved / Peak FLOPS>80% for GEMM

Common Pitfalls

Memory Coalescing

Non-coalesced memory access can reduce bandwidth by 10-32x. Always ensure adjacent threads access adjacent memory addresses.

Shared Memory Bank Conflicts

When multiple threads in a warp access the same bank, access is serialized. Use padding or access patterns to avoid.

Branch Divergence

Divergent branches within a warp execute both paths sequentially. Minimize control flow divergence.

Profiling First

Always profile before optimizing. Use Nsight Compute to identify actual bottlenecks rather than guessing.

Released under the MIT License.